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Campo DC | Valor | Lengua/Idioma |
---|---|---|
dc.contributor.author | Marroquí, David | - |
dc.contributor.author | Garrigós, Ausias | - |
dc.contributor.author | Blanes, Jose M. | - |
dc.contributor.author | Gutiérrez Mazón, roberto | - |
dc.contributor.author | Maset, Enrique | - |
dc.contributor.author | Iannuzzo, Francesco | - |
dc.contributor.other | Departamentos de la UMH::Ingeniería de Comunicaciones | es_ES |
dc.date.accessioned | 2024-01-26T08:47:56Z | - |
dc.date.available | 2024-01-26T08:47:56Z | - |
dc.date.created | 2019-07-12 | - |
dc.identifier.citation | Microelectronics Reliability 100–101 (2019) 113429 | es_ES |
dc.identifier.issn | 0026-2714 | - |
dc.identifier.issn | 1872-941X | - |
dc.identifier.uri | https://hdl.handle.net/11000/30645 | - |
dc.description.abstract | Nowadays, MOSFET SiC semiconductors short circuit capability is a key issue. SiC/Si Cascodes are compound semiconductors that, in some aspects, show a similar MOSFET behaviour. No interlayer dielectric insulation suggests, in theory, Cascode JFETs as more robust devices. The purpose of this paper is to compare the drift and degradation of two commercial devices static parameters by exposing them to different levels of repetitive 1.5 μs short-circuit campaigns at 85% of its breakdown voltage. Short-circuit time has been set experimentally, and longer times result in catastrophic failure of MOSFET devices due to over self-heating. For this purpose, pre- and post-test short circuit characterizations are presented. | es_ES |
dc.format | application/pdf | es_ES |
dc.format.extent | 6 | es_ES |
dc.language.iso | eng | es_ES |
dc.publisher | Elsevier | es_ES |
dc.rights | info:eu-repo/semantics/openAccess | es_ES |
dc.rights | Attribution-NonCommercial-NoDerivatives 4.0 Internacional | * |
dc.rights.uri | http://creativecommons.org/licenses/by-nc-nd/4.0/ | * |
dc.subject.classification | Elecrónica | es_ES |
dc.subject.other | CDU::6 - Ciencias aplicadas::62 - Ingeniería. Tecnología | es_ES |
dc.title | SiC MOSFET vs SiC/Si Cascode short circuit robustness benchmark | es_ES |
dc.type | info:eu-repo/semantics/article | es_ES |
dc.relation.publisherversion | https://doi.org/10.1016/j.microrel.2019.113429 | es_ES |
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