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dc.contributor.authorAlcocer Espinosa, Estefanía Fátima-
dc.contributor.authorGutiérrez Mazón, roberto-
dc.contributor.authorLópez Granado, Otoniel Mario-
dc.contributor.authorPerez Malumbres, Manuel-
dc.contributor.otherDepartamentos de la UMH::Ingeniería de Comunicacioneses_ES
dc.date.accessioned2024-01-26T08:44:48Z-
dc.date.available2024-01-26T08:44:48Z-
dc.date.created2016-02-26-
dc.identifier.citationJournal of Real-Time Image Proc (2019), volume 16, pages 547–557es_ES
dc.identifier.issn1861-8200-
dc.identifier.issn1861-8219-
dc.identifier.urihttps://hdl.handle.net/11000/30643-
dc.description.abstractHigh-Efficiency Video Coding (HEVC) was developed to improve its predecessor standard, H264/AVC, by doubling its compression efficiency. As in previous standards, Motion Estimation (ME) is one of the encoder critical blocks to achieve significant compression gains. However, it demands an overwhelming complexity cost to accurately remove video temporal redundancy, especially when encoding very high-resolution video sequences. To reduce the overall video encoding time, we propose the implementation of the HEVC ME block in hardware. The proposed architecture is based on (a) a new memory scan order, and (b) a new adder tree structure, which supports asymmetric partitioning modes in a fast and efficient way. The proposed system has been designed in VHDL (VHSIC Hardware Description Language), synthesized and implemented by means of the Xilinx FPGA, Virtex-7 XC7VX550T-3FFG1158. Our design achieves encoding frame rates up to 116 and 30 fps at 2 and 4K video formats, respectively.es_ES
dc.formatapplication/pdfes_ES
dc.format.extent11es_ES
dc.language.isoenges_ES
dc.publisherSpringeres_ES
dc.rightsinfo:eu-repo/semantics/openAccesses_ES
dc.rightsAttribution-NonCommercial-NoDerivatives 4.0 Internacional*
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/*
dc.subjectHEVCes_ES
dc.subjectFPGAes_ES
dc.subjectInteger motion estimationes_ES
dc.subjectInter-predictiones_ES
dc.subjectSAD architecturees_ES
dc.subject.classificationElecrónicaes_ES
dc.subject.otherCDU::6 - Ciencias aplicadas::62 - Ingeniería. Tecnologíaes_ES
dc.titleDesign and implementation of an efficient hardware integer motion estimator for an HEVC video encoderes_ES
dc.typeinfo:eu-repo/semantics/articlees_ES
dc.relation.publisherversionhttp//doi.org/10.1007/s11554-016-0572-4es_ES
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