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dc.contributor.authorMarroquí, David-
dc.contributor.authorGarrigós, Ausias-
dc.contributor.authorBlanes, Jose M.-
dc.contributor.authorGutiérrez Mazón, roberto-
dc.contributor.authorMaset, Enrique-
dc.contributor.authorIannuzzo, Francesco-
dc.contributor.otherDepartamentos de la UMH::Ingeniería de Comunicacioneses_ES
dc.date.accessioned2024-01-26T08:47:56Z-
dc.date.available2024-01-26T08:47:56Z-
dc.date.created2019-07-12-
dc.identifier.citationMicroelectronics Reliability 100–101 (2019) 113429es_ES
dc.identifier.issn0026-2714-
dc.identifier.issn1872-941X-
dc.identifier.urihttps://hdl.handle.net/11000/30645-
dc.description.abstractNowadays, MOSFET SiC semiconductors short circuit capability is a key issue. SiC/Si Cascodes are compound semiconductors that, in some aspects, show a similar MOSFET behaviour. No interlayer dielectric insulation suggests, in theory, Cascode JFETs as more robust devices. The purpose of this paper is to compare the drift and degradation of two commercial devices static parameters by exposing them to different levels of repetitive 1.5 μs short-circuit campaigns at 85% of its breakdown voltage. Short-circuit time has been set experimentally, and longer times result in catastrophic failure of MOSFET devices due to over self-heating. For this purpose, pre- and post-test short circuit characterizations are presented.es_ES
dc.formatapplication/pdfes_ES
dc.format.extent6es_ES
dc.language.isoenges_ES
dc.publisherElsevieres_ES
dc.rightsinfo:eu-repo/semantics/openAccesses_ES
dc.rightsAttribution-NonCommercial-NoDerivatives 4.0 Internacional*
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/*
dc.subject.classificationElecrónicaes_ES
dc.subject.otherCDU::6 - Ciencias aplicadas::62 - Ingeniería. Tecnologíaes_ES
dc.titleSiC MOSFET vs SiC/Si Cascode short circuit robustness benchmarkes_ES
dc.typeinfo:eu-repo/semantics/articlees_ES
dc.relation.publisherversionhttps://doi.org/10.1016/j.microrel.2019.113429es_ES
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